1. Technical Field
Embodiments of the invention relate to the field of circuits for data communications encoding, and more specifically to a feed-forward encoder.
2. Background Information and Description of Related Art
A conventional 8B/10B encoder used for encoding signals for data communications is shown in FIG. 1. This encoder is described in U.S. Pat. No. 4,486,739 and in an article entitled “A DC-Balanced Partitioned-Block, 8B/10B Transmission Code,” IBM Journal of Research and Development, Volume 27, Number 5, September 1983, pages 440–451.
The encoder of FIG. 1 maps each incoming source 8-bit character 112 into a 10-bit encoded transmission character 118 based on the contents of the source character 112, a data/control selector bit 114, and a current running disparity. The running disparity of the character being encoded is calculated based on the resulting transmission character and is fed back to be used to encode the next character. The first five bits of each source character are fed into combinatorial logic block 102 that produces partial encodings based on the values of those bits. The last three bits are likewise fed into a similar block 104. These partial encodings are used, in conjunction with the current running disparity from the previous character, to determine how the final encoding should occur to maintain DC balancing of the resulting transmission character stream. This is done by block 106, which uses the partial encodings determined by blocks 102 and 104 and the current running disparity of the previous transmission character. The final encoding is done in combinatorial logic blocks 108 and 110.
A conventional running disparity calculation function 106 is shown in FIG. 2. As shown, the six bits from the 5B functions block 102 and the current running disparity 210 of the previous transmission character are input into combinatorial logic block 202. Combinatorial logic block 202 resolves these seven bits to a single bit, which is then captured in flip-flop 214 on the falling edge of the clock 216. The output of flip-flop 214 tracks the running disparity of the first six bits of the transmission character, and is passed to logic blocks 204 and 206. The output of block 206 is used to control the final encoding of the last four bits of that transmission character. The four bits from the 3B functions block 104 and the running disparity 218 of the first six bits are input into combinatorial logic block 204. Combinatorial logic block 204 resolves these five bits to a single bit, which is then captured in flip-flop 212 on the rising edge of the clock. The output of flip-flop 212 is the running disparity of the entire transmission character, and is passed to logic block 208. The output of block 208 is used to control the final encoding of the first six bits of that transmission character. As shown by the cross-coupling in FIG. 2, it is necessary for one portion of the character to complete evaluation before the next section can begin the encoding process.
An alternative character encoder implementation 300 is shown in FIG. 3a. In this case, the same function shown in FIGS. 1 and 2 is performed in a single clock edge, instead of using a dual-phase clock. A large combinational logic block 302 is placed between the source character 304 and the output transmission character 306. The running disparity 308 is captured by flip-flop 310 once each character time, where it becomes the current running disparity 312 to be used in encoding the following character. The critical path in this implementation is the running disparity calculation of each character.
Due to the finite speed of logic circuits, it is often necessary to encode multiple characters in parallel. FIG. 3b illustrates a character encoder implementation that encodes multiple characters in parallel. The total time gained is effectively the number of characters encoded in parallel minus one, multiplied by the setup and clock-to-out time of the running disparity-tracking flip-flop. However, the delays in this implementation remain dominated by the sequential gating structures used to calculate the running disparity of each character.
FIG. 3c illustrates a character encoder implementation that speeds up a portion of the disparity calculation function when implemented across multiple characters. This implementation is described in U.S. Patent Application No. 60/503,570, filed on Sep. 17, 2003, entitled “Faster 8B/10B Encoding and Decoding on Multi-Byte Datapath.” In this implementation, one encoder for each character in the data path generates the new transmission character assuming the previous one ended with positive running disparity, and another encoder generates the new transmission character assuming the previous one ended with negative running disparity. A multiplexer is used to select one of each of the generated pairs of transmission characters. This allows the encode function to occur in parallel on multiple characters and reduces the critical path to the delay of the running disparity calculation of the first character plus the delay through successive multiplexers of the remaining characters in the data path. However, this implementation requires the number of encoders to be doubled, the number of running disparity calculation circuits to be doubled, and adds multiple 11-bit-wide 2:1 multiplexers.